Zilog Z08470 Bedienungsanleitung PDF herunterladen (Seite 84)

UM008101-0601 Direct Memory Access

when M1 occurs without an active RD or IORQ for at least two clock

cycles, the internal reset is activated at the falling clock after M1 returns to

the inactive state. This internal reset lasts for three clock cycles.

MREQ

Memory Request (output, active Low, tristate). This line indicates that the

address bus contains a valid address for a memory read or write operation.

After the DMA has taken control of the system buses, it indicates a DMA

transfer request from or to memory.

Read (bidirectional, active Low, tristate). As an input, this signal indicates

that the CPU is ready to read status bytes from the DMAs read registers. As

an output, after the DMA has taken control of the system buses, it indicates

a DMA-controlled read from memory or I/O port address.

RDY

Ready (input, programmable active Low or High). This pin is monitored by

the DMA to determine when a peripheral device associated with a DMA

port is ready for a read or write operation. When the DMA is enabled to

operate, the RDY line indirectly controls DMA activity; the manner in

which DMA activity is controlled by RDY

depends on what operating

mode is selected (Byte, Burst, or Continuous). An active RDY

line can be

simulated by programming a Force Ready condition. This is useful in

memory-to-memory operations. It is preferable to have the RDY

signal

synchronized to the CLK signal, for example, RDY should become active

on the rising edge of CLK. This is particularly important in the Continuous

mode of operation.

Write (bidirectional, active Low, tristate). As an input, this indicates that the

CPU is requesting to write control bytes to the DMA write registers when

the DMA is selected. As an output, after the DMA has taken control of the

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Zilog Z08470 Bedienungsanleitung Seite 84