Zilog Z08470 Bedienungsanleitung PDF herunterladen (Seite 170)

100

101

UM008101-0601 Direct Memory Access

Figure 59. CPU-to-DMA Write Cycle Requirements

To write to the DMA control bites, the following conditions must be met:

•

The DMA’s CE line must be Low (normally done by decoding the

lower byte of the address bus).

•

The IORQ and WR lines must be Low at this time.

•

The control byte must be placed on the data bus so that it is stabilized

at a rising clock edge, which occurs one clock period after the CE,

IORQ,andWRlines have stabilized.

Reading Status Bytes

Figure 60 illustrates the timing needed for the CPU to read the DMA’s read

registers, RR6 through RR0, while the CPU is bus master. To read a regis-

ter, this condition must be met: The CE

,IORQ,andRDlines must be

active and stabilized over two rising edges of the clock.

Status data becomes available on the data bus at the time of the second

clock rising edge, which remains on the bus for as long as both the CE

IORQ

,andRDlines remain active.

CLK

IORQ

D7–D0

1 2 ... 165 166 167 168 169 170 171 172 173 174 175 ... 329 330

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