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101

UM008101-0601 Direct Memory Access

Figure 64. Simultaneous Memory-to-I/O Transfer (Byte Mode)

Figure 63 illustrates the timing for simultaneous transfers in Burst and Con-

tinuous modes between memory and I/O, using standard Z80 timing. The

timing within each cycle is similar to the memory read cycle shown in

Figure 61. The address bus activity is the same, and the cycle length is the

same. However, the MREQ

,RD,IORQ,andWRlines in Figure 61 have

been changed to MEMRD and IOWR lines in Figure 63. In addition, the

data bus becomes active earlier in Figure 63, in response to the MEMRD

line becoming active. Data is clocked to the l/O port on the rising edge of

IOWR

Figure 64 depicts the timing for Byte mode. Timing is identical to

Figure 63 within each cycle. The breaks between each cycle, where the

address and data bus are tristated and the MEMRD

and IOWR lines remain

CE/WAIT

A15–A0

CLK

D7–D0

IOWR

MEMRD

ycle 2

DMA Drives

the Last Data

it Read During

this Time

Cycle 1

1 2 ... 171 172 173 174 175 176 177 178 179 180 181 ... 329 330

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