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ZiLOG Z08470 Handbücher

Bedienungsanleitungen und Benutzerhandbücher für Sensoren ZiLOG Z08470.
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Zilog Z08470 Bedienungsanleitung (326 Seiten)


Marke: Zilog | Kategorie: Sensoren | Größe: 1.33 MB |

 

Inhaltsverzeichnis

Z80 Microprocessors

1

LIFE SUPPORT POLICY

2

As used herein

2

Document Disclaimer

2

Revision History

3

Table of Contents

4

List of Figures

10

User Manual

11

List of Tables

12

Architectural Overview

13

CPU Register

14

Special-Purpose Registers

14

General Purpose Registers

15

Arithmetic Logic Unit

16

Pin Description

16

Pin Functions

17

• Memory read or write

19

• I/O device read or write

19

• Interrupt acknowledge

19

Instruction Fetch

20

Memory Read Or Write

21

Input or Output Cycles

22

Bus Request/Acknowledge Cycle

23

HALT Exit

26

Power-Down Acknowledge Cycle

27

Power-Down Release Cycle

28

Interrupt Response

29

CPU Response

31

Minimum System Hardware

33

Adding RAM

34

Memory Speed Control

35

Example 1

39

Example 2

39

Example 3

39

Example 4

40

Programming Task Examples

41

Programming Task Examples

43

Z80 CPU Instructions

44

Addressing Modes

46

Addressing

46

Register Addressing

49

Implied Addressing

49

Register Indirect Addressing

49

One or Two Bytes

49

Instruction Op Codes

50

Load and Exchange

51

Table 5. 8-Bit Load Group LD

52

+8 is written as:

53

Top of stack

56

• BC is a byte counter

57

Table 9. Block Search Group

59

Table 12. 16-Bit Arithmetic

62

Rotate and Shift

63

Figure 39. Rotates and Shifts

64

Bit Manipulation

67

3E32h is shown in Figure 40

68

UM008007-0715 Input/Output

71

Table 16. Restart Group

71

Table 17. Input Group

72

Z80 Instruction Set

75

Carry Flag

76

Add/Subtract Flag

76

Parity/Overflow Flag

77

Half Carry Flag

78

Zero Flag

78

Z80 Instruction Description

79

8-Bit Load Group

80

LD r, r'

81

00 r 101

82

LD r, (HL)

84

LD r, (IX+d)

85

LD r, (IY+d)

87

LD (HL), r

89

LD (IX+d), r

91

LD (IY+d), r

93

LD (HL), n

95

LD (IX+d), n

96

LD (IY+d), n

97

LD A, (BC)

98

LD A, (DE)

99

LD A, (nn)

100

LD (BC), A

101

LD (DE), A

102

LD (nn), A

103

11 0 01111

104

01 1 11100

104

01 1 11101

105

01 0 11100

106

01 0 11101

107

16-Bit Load Group

108

LD dd, nn

109

LD IX, nn

110

LD IY, nn

111

LD HL, (nn)

112

LD dd, (nn)

113

LD IX, (nn)

115

LD IY, (nn)

116

LD (nn), HL

117

LD (nn), dd

118

Z80 Instruction Description

119

LD (nn), IX

120

LD (nn), IY

121

LD SP, HL

122

LD SP, IX

123

LD SP, IY

124

11 q 011q0

125

11 1 01101

127

11 0 01110

127

11 1 01111

128

11 q 010q0

129

11 0 01010

131

EX DE, HL

134

EX AF, AF′

135

11 1 01001

136

EX (SP), HL

137

EX (SP), IX

138

EX (SP), IY

139

10 0 00010

140

↔ BC – 1

142

10 1 00010

142

10 0 00011

144

10 1 00011

146

Condition Bits Affected

147

10 1 01010

149

10 0 01011

151

10 1 01011

152

8-Bit Arithmetic Group

154

ADD A, r

155

ADD A, n

157

ADD A, (HL)

158

ADD A, (IX + d)

159

ADD A, (IY + d)

160

ADC A, s

161

Description

162

Operation

163

SBC A, s

165

00 r 001

175

INC (HL)

177

INC (IX+d)

178

INC (IY+d)

179

Control Groups

182

00 0 11110

183

00 0 11111

185

01 0 00100

186

10 1 00001

187

01 0 00011

187

00 1 11111

188

00 1 11110

189

00 0 00000

190

01 1 10110

191

11 1 11010

192

11 1 11011

193

01 0 10100

194

01 1 10100

195

01 1 10101

196

16-Bit Arithmetic Group

197

ADD HL, ss

198

ADC HL, ss

200

SBC HL, ss

202

ADD IX, pp

204

ADD IY, rr

206

00 s 110s0

208

00 0 11010

209

00 s 110s1

211

00 0 11011

212

Rotate and Shift Group

214

00 0 11100

215

00 1 11100

217

00 0 11101

219

00 1 11101

221

11 0 11001

223

RLC (HL)

225

and the Carry

226

RLC (IX+d)

227

RLC (IY+d)

229

10 0 11101

232

76 4 10253

232

00 1 10101

233

00 1 01010

235

001010 01

236

101110 11

238

011101 10

239

01 0 10010

242

001110 11

245

01 0 11111

248

01 0 11110

250

BIT b, r

253

BIT b, (HL)

255

BIT b, (IX+d)

257

BIT b, (IY+d)

259

SET b, r

261

SET b, (HL)

263

SET b, (IX+d)

265

SET b, (IY+d)

266

RES b, m

268

Jump Group

270

11 0 11000

271

JP cc, nn

272

00 1 00001

274

PC after jump

275

00 1 00011

276

JR NC, e

278

00 0 00011

280

JR NZ, e

282

11 0 01011

284

00 1 00000

287

Call and Return Group

289

11 0 01101

290

CALL cc, nn

292

11 0 01001

294

01 0 01101

297

01 0 01100

299

11 t 111

301

Input and Output Group

303

IN A, (n)

304

IN r (C)

305

10 0 10010

307

10 1 10010

309

10 0 10011

311

10 1 10011

313

OUT (n), A

315

OUT (C), r

316

10 0 11010

318

10 1 11010

320

10 0 11011

322

10 1 11011

324

Customer Support

326

Zilog Z08470 Bedienungsanleitung (330 Seiten)


Marke: Zilog | Kategorie: Sensoren | Größe: 2.29 MB |

 

Inhaltsverzeichnis

Z80 Family

1

CPU Peripherals

1

Table of Contents

3

Direct Memory Access

4

List of Figures

9

UM008101-0601 List of Figures

10

List of Figures UM008101-0601

11

Parallel Input/Output

12

Serial Input/Output

13

List of Tables

15

List of Tables UM008101-0601

17

Z80 CPU Peripherals

18

User Manual

18

Counter/Timer Channels

19

CTC ARCHITECTURE

20

Structure of Channel Logic

21

The Prescaler

23

Interrupt Control Logic

25

CTC PIN DESCRIPTION

27

CTC OPERATING MODES

34

CTC COUNTER Mode

34

CTC TIMER Mode

35

CTC PROGRAMMING

36

Table6.TimeConstantRegister

40

76543210

40

CTC Read Cycle

43

CTC Counting and Timing

44

CTC INTERRUPT SERVICING

45

Return from Interrupt Cycle

47

DMA Data Transfers

53

DMA Characteristics

55

Transfer Methods

56

Modes of Operation

58

Bus Control

59

Programmability

59

Figure 17. Modes of Operation

60

Programming

63

Classes of Operation

64

<%2 72GTKRJGTCNU

65

7UGT/CPWCN

65

<%272GTKRJGTCNU

66

Figure 20)

70

Transfer Speed

74

Address Generation

75

Variable Cycle

78

Events and Actions

79

I/O port address

85

,17(51$/6758&785(

89

*HQHUDO2UJDQL]DWLRQ

89

Address and Byte Counting

93

Operations)

94

Search Operations)

94

Bus Requesting

96

Bus Request Daisy-Chains

97

Interrupt Vectors

100

Interrupt Latches

102

Interrupt On Ready

104

Interrupt Service Routines

104

Return From Interrupt

105

Interrupt Daisy-Chains

106

Polling for Service Requests

107

PROGRAMMING

108

Overview

108

Table 13. DMA Status

109

DISABLED ENABLED

109

Write Registers

110

Write Register 0 Group

111

Source and Destination

112

Port A Starting Address

112

Block Length

113

Write Register 1 Group

114

Write Register 2 Group

116

Write Register 3 Group

116

Stop on Match

117

Match Byte

117

Mask Byte

117

Interrupt Enable

117

Write Register 4 Group

118

Starting Address (Port B)

119

Interrupts

119

Interrupt Vector

120

Pulse Generation

120

Write Register 5 Group

121

End-of-Block Action

122

CE/WAIT Line Use

122

Ready-Line State

122

Reset (C3)

123

ResetPortATiming(C7)

124

ResetPortBTiming(CB)

124

Load (CF)

124

Continue (D3)

125

Disable Interrupts (AF)

125

Enable Interrupts (AB)

127

Enable After RETI (B7)

128

Read Status Byte (BF)

129

Reinitialize Status Byte (8B)

129

Read Mask Follows (BB)

130

Initiate Read Sequence (A7)

131

Force ReadY (B3)

131

Read Registers

132

Read Status Byte

133

Initiate Read Sequence

133

Reinitialize Status Byte

133

Read Mask Follows

133

Status Byte (RR0)

133

Byte Counter (RR1, RR2)

135

DMA Initialization

136

Port Designation

138

Address Loading

139

Byte Matching (Searches)

142

End-of-Block

143

Auto Restart

143

Force Ready Condition

143

Variable Timing

144

Enabling the DMA

144

Reading Status

144

Z80 DMA and CPU

147

Chip Selection and Enabling

148

Use of WAIT Input

150

Simultaneous Transfers

151

Bus Buffering

154

Z80 DMA and Z80 SIO Example

157

Table 18

158

Bus Characteristics

163

PERFORMANCE LIMITATIONS

167

Bus Contention

167

Control Overhead

168

The CPU As Bus Master

169

Reading Status Bytes

170

The DMA As Bus Master

171

(Searching is Optional)

174

Search-Only

177

Bus Requests

177

Bus Release Byte-at-a-Time

178

Bus Release on End-of-Block

179

Bus Release on Match

180

Bus Release on Not Ready

180

REGISTER BIT FUNCTIONS

189

Write Register Bit Functions

189

Read Register Bit Functions

193

Figure 1. PIO Block Diagram

197

Data Input

198

(8 Bits)

198

PIN DESCRIPTION

200

Figure 3. PIO Pin Functions

204

PROGRAMMING THE PIO

207

Loading The Interrupt Vector

208

SelectingAnOperatingMode

209

D6 D5 D4 D3 D0D2 D1

210

Output Mode (Mode 0)

212

Input Mode (Mode 1)

213

Bidirectional Mode (Mode 2)

214

Control Mode (Mode 3)

215

INTERRUPT SERVICING

217

APPLICATIONS

219

I/O Device Interface

220

V3 V2 V1 V0

221

Control Interface

222

PROGRAMMING SUMMARY

225

Load Interrupt Vector

225

Set Mode

225

Set Interrupt Control

226

Pin Functions

230

Bonding Options

233

CMOS Z80

240

ARCHITECTURE

242

Data Path

243

Functional Description

246

I/O Capabilities

247

ASYNCHRONOUS OPERATION

250

Asynchronous Transmit

252

Asynchronous Receive

255

SYNCHRONOUS OPERATION

258

Monosync

260

External Sync

260

Synchronous Transmit

264

Synchronous Receive

269

SDLC (HDLC) OPERATION

275

SDLC Transmit

276

SDLC Receive

285

0001 1101 0000 1111

287

Write Register 0

293

Figure 114. Write Register 0

294

Write Register 1

297

Write Register 2

301

Write Register 3

302

Write Register 4

304

Write Register 5

307

Write Register 6

310

Write Register 7

311

Figure 122. Read Register 0

314

Read Register 1

317

Figure 123. Read Register 1

319

Table 35. Interrupt Vector

320

D7 D6 D5 D4 D3 D2 D1 D0

320

V7 V6 V5 V4 V3* V2* V1* V0

320

Figure 127. Data Concentrator

324

Read Cycle

325

Write Cycle

325

Interrupt Acknowledge Cycle

326

Return From Interrupt Cycle

327

Daisy Chain Interrupt Nesting

328




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