Zilog Z80180 Bedienungsanleitung PDF herunterladen (Seite 315)

Z8018x

Family MPU User Manual

UM005003-0703

299

DMA Memory Address

Register

Channel 1B:

DMA I/O Address Register

Channel 1L:

DMA I/O Address Register

Channel 1H

DMA Byte Count Register

Channel 1L:

DMA Byte Count Register

Channel 1H:

DMA Status Register:

DMA Mode Register:

MAR1B

IAR1L

IAR1H

BCR1L

BCR1H

DSTAT

DMODE

2A

2B

2C

2E

2F

30

31

Table 57. Internal I/O Registers (Continued)

Register Mnemonics Address Remarks

DE1 DE0 DWE0 DIE1 DIE0 — DME

R/W

R/WR/W W W R

DMA Enable Bit Write Enable 1,0

DMA enable ch 1,0

0

0

101 010

bit

during RESET

R/W

DMA Master enable

DMA Interrupt Enable 1,0

DM1,0

0 0

0 1

1 0

1 1

M

M

I/O

M

Destination

DWE1

Address

DAR0+1

DAR0-1

DAR0 fixed

DAR0 fixed

— — DM0SM1 SM0MMOD —

R/WR/W R/W R/W

Ch 0 Destination Mode 1,0

0

1

010 001

bit

during RESET

R/W

Memory MODE select

Ch 0 Source Mode 1,0

DM1

R/W

SM1,0

0 0

0 1

1 0

1 1

M

M

I/O

M

Source

Address

SAR0+1

SAR0-1

SAR0 fixed

SAR0 fixed

MMOD Mode

0

1

Cycle Steal Mode

Burst Mode

R/W

Bits 0 - 2 are used for MAR1B

1 2 ... 310 311 312 313 314 315 316 317 318 319 320 ... 325 326

Kommentare zu diesen Handbüchern

Keine Kommentare