Zilog Z80180 Bedienungsanleitung PDF herunterladen (Seite 184)

100

101

Z8018x

Family MPU User Manual

UM005003-0703

169

If an external clock input is used instead of a crystal, the waveform (twice

the clock rate) must exhibit a 50% ± 10% duty cycle.

The minimum clock input High voltage level is V

–0.6V. The

external clock input is connected to the EXTAL pin, while the

XTAL pin is left open. Figure 70 depicts the external clock

interface.

Figure 70. External Clock Interface

Figure 71 illustrates the Z8X180 clock generator circuit while Figures 72

and 72 specify circuit board design rules.

Table 25. Z8X180 Operating Frequencies

4MHz

< f £ 12MHz 12MHz < f £ 33MHz

< 7 pF < 7 pF < 7 pF

<60W<60W<60W

CL1, CL2 10 to 22 pF ± 10% 10 to 22 pF ± 10% 10 to 22 pF ± 10%

Clock

Item

Frequency

Note:

EXTAL

XTAL

Open

External Clock Input

1 2 ... 179 180 181 182 183 184 185 186 187 188 189 ... 325 326

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