
Z8018x
Family MPU User Manual
UM005003-0703
xv
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Family MPU
1
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MANUAL OBJECTIVES
3
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Intended Audience
3
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Manual Organization
3
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Sections
4
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Appendices
4
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Table of Contents
5
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List of Figures
8
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UM005003-0703
10
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List of Tables
12
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Status Signals 287
14
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FEATURES
16
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GENERAL DESCRIPTION
16
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PIN DESCRIPTION
22
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ARCHITECTURE
27
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OPERATION MODES
30
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0 and IOC is 0
32
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CPU Timing
33
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Wait State Generator
42
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Bit 7 6 5 4
44
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MWI1 MWI0 MWI1 MWI0
44
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R/W R/W R/W R/W
44
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1, selecting the
45
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Processors Only)
46
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SLP 2nd Op Code address
50
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Add-On Features
51
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STANDBY Mode
52
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IDLE Mode
55
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STANDBY-QUICK RECOVERY Mode
56
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Internal I/O Registers
56
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–0 Reserved ? ? Reserved
67
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Memory Management Unit (MMU)
69
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Figure 25. MMU Block Diagram
71
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0 during I/O cycles
72
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MMU Register Description
75
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0 during RESET
77
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1 while all bits
78
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0. The logical 64KB
78
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0000H to FFFFH)
78
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Interrupts
80
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Interrupt Vector Low Register
81
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00H during RESET
82
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N/A R/W R/W R/W
83
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1 by the El (Enable
84
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00000H was caused by
85
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INT0 Mode 0
90
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INT0 Mode 1
91
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INT0 Mode 2
93
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00H and
94
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INT1, INT2
95
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0. Each is also
96
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Family MPU User Manual
100
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Dynamic RAM Refresh Control
101
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TR1 TRW* TR2
102
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DMA Controller (DMAC)
105
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107
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DMAC Register Description
108
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DMA Register Description
118
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Bits 5–3
119
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Bits 2–0
119
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DMA Operation
119
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Memory to Memory—Channel 0
120
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00H) transfer
122
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Memory to ASCI - Channel 0
124
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Note: X = Don’t care
125
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T1 T2 T3 T3T2T1
130
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Processors
131
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ASCI Register Description
132
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08H, 09H)
134
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1) these pins
149
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1, then the CKA1/
149
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0. Even after the
154
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Figure 56. ASCI Clock
156
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Baud Rate Generator
158
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CSI/O Block Diagram
161
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CSI/O Registers Description
162
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Address = 0BH)
164
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Interrupt Request
166
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= 0) when
167
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PRT Block Diagram
171
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PRT Register Description
172
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0FH, CHI, 16H, 17H)
174
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Timer Control Register (TCR)
176
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PRT Interrupts
179
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PRT and RESET
179
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Secondary Bus Interface
180
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On-Chip Clock Generator
183
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Miscellaneous
187
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Software Architecture
188
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CPU REGISTERS
190
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Accumulator (A, A')
191
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Flag Registers (F, F')
192
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Interrupt Vector Register (I)
192
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R Counter (R)
192
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Index Registers (IX, and IY)
192
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Stack Pointer (SP)
193
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Program Counter (PC)
193
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Flag Register (F)
193
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Addressing Modes
195
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Implied Register (IMP)
195
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Register Direct (REG)
195
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Register Indirect (REG)
196
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Indexed (INDX)
197
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Extended (EXT)
197
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Immediate (IMMED)
198
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Relative (REL)
198
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IO (I/O)
199
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DC Characteristics
200
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Z80180 DC CHARACTERISTICS
201
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Z8S180 DC CHARACTERISTICS
202
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Z8L180 DC CHARACTERISTICS
204
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AC Characteristics
208
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Timing Diagrams
213
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STANDARD TEST CONDITIONS
221
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Instruction Set
223
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CONDITION
224
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RESTART ADDRESS
225
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MISCELLANEOUS
226
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DATA TRANSFER INSTRUCTIONS
238
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Special Control Instructions
251
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Instruction Summary
253
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Op Code Map
263
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DDH 22H : LD (mn), IX
264
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Bus Control Signal Conditions
267
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INTERRUPTS
295
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Operating Modes Summary
297
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REQUEST PRIORITY
298
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OPERATION MODE TRANSITION
299
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0000H (all DMA transfers)
301
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Status Signals
303
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PIN STATUS
304
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–A17, A19 — Z 1 A 1
305
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–D7— ZZAZ
305
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INTERNAL I/O REGISTERS
309
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Ch 0 Destination Mode 1,0
315
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ORDERING INFORMATION
319
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