Zilog Z80180 Bedienungsanleitung PDF herunterladen (Seite 24)

Z8018x

Family MPU User Manual

UM005003-0703

BUSREQ, and INT0 signals are inactive. The CPU acknowledges these

interrupt requests with an interrupt acknowledge cycle. Unlike the

acknowledgment for INT

0, during this cycle neither the M1 or IORQ

signals become Active.

IORQ

. I/O Request (Output, Active Low, 3-state). IORQ indicates that the

address bus contains a valid I/O address for an I/O read or I/O write

operation. IORQ

is also generated, along with M1, during the

acknowledgment of the INT

0 input signal to indicate that an interrupt

response vector can be placed onto the data bus. This signal is analogous

to the IOE

signal of the Z64180.

1. Machine Cycle 1 (Output, Active Low). Together with MREQ, M1

indicates that the current cycle is the Op Code fetch cycle of an

instruction execution. Together with IORQ

, M1 indicates that the current

cycle is for an interrupt acknowledge. It is also used with the HALT

and

ST signal to decode status of the CPU machine cycle. This signal is

analogous to the LIR

signal of the Z64180.

MREQ

. Memory Request (Output, Active Low, 3-state). MREQ indicates

that the address bus holds a valid address for a memory read or memory

write operation. This signal is analogous to the ME

signal of the Z64180.

NMI

. Non-maskable Interrupt (Input, negative edge triggered). NMI has

a higher priority than INT

and is always recognized at the end of an

instruction, regardless of the state of the interrupt enable flip-flops. This

signal forces CPU execution to continue at location

0066H.

. Read (Output active Low, 3-state). RD indicates that the CPU wants

to read data from memory or an I/O device. The addressed I/O or memory

device must use this signal to gate data onto the CPU data bus.

RFSH

. Refresh (Output, Active Low). Together with MREQ, RFSH

indicates that the current CPU machine cycle and the contents of the

address bus must be used for refresh of dynamic memories. The low order

8 bits of the address bus (A7–A0) contain the refresh address.

This signal is analogous to the REF

signal of the Z64180.

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