Zilog Z8F0130 Bedienungsanleitung PDF herunterladen (Seite 43)

eZ8

™

CPU Core

User Manual

UM012820-0810 Interrupts

Interrupt Priority

The Interrupt Controller prioritizes all interrupts. Refer to the Zilog Prod-

uct Specification specific to your Z8 Encore! device for information about

the Interrupt Controller.

Vectored Interrupt Processing

Each eZ8 CPU interrupt is assigned its own vector. When an interrupt

occurs, control passes to the interrupt service routine pointed to by the

interrupt’s vector location in Program Memory. The sequence of events

for a vectored interrupt is as follows:

1. Push the low byte of the Program Counter, PC[7:0], on the stack.

2. Push the high byte of the Program Counter, PC[15:8], on the stack.

3. Push the Flags Register on the stack.

4. Fetch the High Byte of the Interrupt Vector.

5. Fetch the Low Byte of the Interrupt Vector.

6. Branch to the Interrupt Service Routine specified by the Interrupt

Vector.

Figure 17 displays the effect of vectored interrupts on the Stack Pointer

and the contents of the stack. Figure 18 provides an example of the

Program Memory during interrupt operation. In Figure 18, the Interrupt

Vector is located at address

0014h in Program Memory. The 2-byte

Interrupt Vector, stored at Program Memory addresses

0014h and 0015h,

is loaded into the Program Counter. Execution of the Interrupt Service

Routine begins at Program Memory address

4567h, as is stored in the

Interrupt Vector.

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Zilog Z8F0130 Bedienungsanleitung Seite 43