
eZ8
™
CPU Core
User Manual
UM012820-0810 TCM Instruction
241
ment resets the Z flag (because bit 3 in the destination operand is not a 1)
and clears the V and S flags:
TCM R14, @R5
Object Code: 63 E5
If Register D4h contains the value 04h (00000100b), and Working Reg-
ister R0 contains the value 80h (10000000b) (testing bit 7 it is 1), the
following statement resets the Z flag (because bit 7 in the destination
operand is not a 1), sets the S flag, and clears the V flag:
TCM
D4h
, R0
Object Code: 64 E0 D4
If Register DFh contains the value FFh (11111111b), Register 07h con-
tains the value 1Fh, and Register 1Fh contains the value BDh
(
10111101b; testing bits 7, 5, 4, 3, 2, and bit 0 if they are 1), the follow-
ing statement sets the Z flag (indicating the tested bits in the destination
operand are 1) and clears the S and V flags:
TCM
DFh
, @
07h
Object Code: 65 07 DF
If Working Register R13 contains the value F2h (11110010b), the fol-
lowing statement tests bit 1 of the destination operand for 1, sets the Z
flag (indicating bit 1 in the destination operand was 1) and clears the S
and V flags:
TCM R13, #02h
Object Code: 66 ED, 02
If Register 5Dh contains the value A0h, and Register A0h contains the
value
0Fh (00001111b), the following statement tests bit 4 of the Regis-
ter A0h for 1, resets the Z flag (indicating bit 4 in the destination operand
was not 1), and clears the S and V flags:
TCM @5D, #
10h
Object Code: 67 5D 10
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