ZiLOG Z16C35 Handbücher

Zilog Z16C35 Bedienungsanleitung (322 Seiten)

Marke: Zilog | Kategorie: Sensoren | Größe: 3.13 MB |

Englisch

Inhaltsverzeichnis

User Manual

1

Revision History

3

Table of Contents

4

1.1 INTRODUCTION

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Page 2 of 316

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Page 3 of 316

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1.3 Pin Description

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2.1 Introduction

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Page 12 of 316

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2.2.3 Data Transfers

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2.3.1 Polling

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2.3.2 Interrupts

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2.3.3 DMA Interrupts

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2.4 REGISTER ACCESS

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2.4.4 DMA Cell Registers

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Support Circuitry

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3.3 BAUD RATE GENERATOR

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3.4 DATA ENCODING/DECODING

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3.6 CLOCK SELECTION

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3.7 CRYSTAL OSCILLATORS

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4.2 ASYNCHRONOUS MODE

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4.2.1 Asynchronous Transmit

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WR4 0,1 select parity

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WR5 1 RTS

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2 select CRC generator

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4.4.1 SDLC Transmit

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WR4 1-0 Select parity

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WR5 2 Select CRC-CCITT

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4.4.2 SDLC Receive

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4.4.3 SDLC LOOP MODE

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5.1 INTRODUCTION

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5.2 REGISTER DESCRIPTIONS

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5.2.3 DMA Registers

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5.4 WRITE REGISTERS

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Mode Definition)

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Constant)

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5.5 READ REGISTERS

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5.5.2 Read Register 1

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5.5.3 Read Register 2

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5.5.4 Read Register 3

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5.5.5 Read Register 8

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5.5.6 Read Register 10

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5.5.7 Read Register 12

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5.5.8 Read Register 13

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5.5.9 Read Register 15

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5.6.2 DMA Status Register

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5.6.7 DMA Enable Register

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5.6.8 DMA Control Register

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UM011002-0808

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Customer Support

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PPLICATION

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Write Cycle Timing

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INPUT/OUTPUT CYCLES

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Z80A CPU to Z8500 Peripherals

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INPUT/OUTPUT CYCLES

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(Continued)

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Z90H CPU TO Z8500 PERIPHERALS

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INTERRUPT ACKNOWLEDGE CYCLES

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EXTERNAL INTERFACE LOGIC

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CPU/Peripheral Same Speed

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Z8500/Z8500A Peripherals

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Software

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Interfacing Z80

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INTRODUCTION

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INTERFACES

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Z180 to Memory Interface

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EPROM INTERFACE

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'74 '74

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Z180 TO I/O INTERFACE

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(Continued)

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SCC Interrupt Operation

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Z180 MPU to SCC Interface

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SCC I/O Read/Write Cycle

191

USING EPLD

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Application Note

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CONCLUSION

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GENERAL DESCRIPTION

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GENERAL DESCRIPTION

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Processor

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Address Map

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UM011001-0601

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IUSC (Continued)

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SERIAL INTERFACING

220

JUMPER SUMMARY

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DMA/EPLD LOGIC

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DMA/EPLD LOGIC (Continued)

228

YNCHRONOUS

231

OMMUNICATIONS

231

SYNCHRONOUS MODES

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SYSTEM INTERFACE

232

CONTROL BUS

233

EPROM CONTROL BUS

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RAM CONTROL BUS

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ADDRESS/DATA BUS

233

SYSTEM INTERFACE

234

INITIALIZATION

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INITIALIZATION

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APPENDIX

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SOFTWARE ROUTINES

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RECEIVE ROUTINE

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TRANSMIT ROUTINE

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RECEIVE INT. SERVICE ROUTINE

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SDLC TRANSMIT

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SDLC RECEIVE

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/W//REQ (In /REQ mode)

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ONLY MODE

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Master SCC

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Slave SCC #1

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Slave SCC #2

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Slave SCC #n

253

DATA TRANSFER MODES

256

SDLC PROTOCOL

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TRANSMIT OPERATION

262

RECEIVE OPERATION

262

SOFTWARE

265

RECEIVE OPERATION

267

ESCC/SCC DIFFERENCES

269

ESCC SYSTEM BENEFITS

271

TRANSMIT FIFO INTERRUPT

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RECEIVE FIFO INTERRUPT

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AUTOMATIC /RTS DEASSERTION

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MODIFIED WRITE TIMING

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HARDWARE CONFIGURATION

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TRANSMITTING A LLAP FRAME

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RECEIVING LLAP FRAMES

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CONCLUSIONS

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APPENDIX A

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APPENDIX B

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SCILLATOR

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Quartz Equivalent Circuit

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Symbolic Representation

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Load Capacitors

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Amplifier Characteristics

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Signal Line

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Layout Should

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Avoid High

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Lighted Areas

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NTERFACING

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CONFIGURING THE BUS

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APPLICATIONS EXAMPLES

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ONTROLLER

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ISCC QUESTIONS AND ANSWERS

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