Zilog Z16C35 Bedienungsanleitung PDF herunterladen (Seite 141)

ISCC

User Manual

UM011002-0808

135

5.6.5 Interrupt Command Register

This is a write only register and is used to command the DMA cell. It shares its address

with the Interrupt Status Register. The bit positions for the Interrupt Command Register

are shown in Figure 5-30.

Figure 5–59. Interrupt Command Register

Bits 7 through 5 are encoded with the commands for the DMA cell as shown below:

Bit combination 000 is a Null command and has no affect on the DMA.

Bit combination 001 resets the Interrupt Pending (IP) bit in the selected DMA channel(s).

Bit combination 010 resets the Interrupt Under Service (IUS) bit in the selected DMA

channel(s).

Bit combination 011 resets both the Interrupt Pending (IP) bit and the Interrupt Under Ser-

vice (IUS) bit in the selected DMA channel(s).

Bit combination 100 is Reserved.

Bit combination 101 sets the Interrupt Pending (IP) bit in the selected DMA channel(s).

Bit combination 110 sets the Interrupt Under Service (IUS) bit in the selected DMA chan-

nel(s).

Bit combination 111 sets both the Interrupt Pending (IP) bit and the Interrupt Under Ser-

vice (IUS) bit in the selected DMA channel(s).

Address: 00011 (Write)

D6D7

D5 D4 D3 D2 D1 D0

Select Tx B DMA

Select Rx B DMA

Select Tx A DMA

Select Rx A DMA

Reserved

Null Comand

Reset IP

Reset IUS

Reset IP and IUS

Reserved

Set IP

Set IUS

Set IP and IUS

DMA Interrupt Commands

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