Zilog Z16C35 Bedienungsanleitung PDF herunterladen (Seite 47)

100

101

ISCC

User Manual

UM011002-0808

Figure 3–12. Clock Multiplexer

Selection of the clocking options may be done anywhere in the initialization sequence, but

the final values must be selected before the receiver, transmitter, baud rate generator, or

DPLL are enabled to prevent problems from arbitrarily narrow clock signals out of the

multiplexers. The same is true of the crystal oscillator, in that the output should be allowed

to stabilize before it is used as a clock source.

Also shown are the edges used by the receiver, transmitter, baud

rate generator and DPLL

to sample or send data or otherwise change state. For example, the receiver samples data

on the falling edge, but since there is an inversion in the clock path between the /RTxC pin

and the receiver, a rising edge of the /RTxC pin samples the data for the receiver.

OSC

/SYNC

/RTxC

OSC

Receiver

DPL

BRG

/TRxC

Baud Rate

Generator Out

Tx DPLL Out

Rx DPLL Out

PCL

Echo

Baud Rate

Generator

DPPL

Transmitter

Echo

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