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Application Note

SCC in Binary Synchronous Communications

10-5

When the Z8002 CPU uses the lower half of the

Address/Data bus (AD0-AD7 the least significant byte) for

byte read and write transactions during I/O operations,

these transactions are performed between the CPU and

I/O ports located at odd I/O addresses. Since the Z-SCC is

attached to the CPU on the lower half of the A/D bus, its

registers must appear to the CPU at odd I/O addresses. To

achieve this, the Z-SCC can be programmed to select its

internal registers using lines AD5-AD1. This is done either

automatically with the Force Hardware Reset command in

WR9 or by sending a Select Shift Left Mode command to

WR0B in channel B of the Z-SCC. For this application, the

Z-SCC registers are located at I/O port address ‘FExx’.

The Chip Select signal (/CS0) is derived by decoding I/O

address ‘FE’ hex from lines AD15-AD8 of the controller.

The Read/Write registers are automatically selected by the

Z-SCC when internally decoding lines AD5-AD1 in Shift

Left mode. To select the Read/Write registers

automatically, the Z-SCC decodes lines AD5-AD1 in Shift

Left mode. The register map for the Z-SCC is depicted in

Table 1.

INITIALIZATION

The Z-SCC can be initialized for use in different modes by

setting various bits in its Write registers. First, a hardware

reset must be performed by setting bits 7 and 6 of WR9 to

one; the rest of the bits are disabled by writing a logic zero.

Bisync mode is established by selecting a 16-bit sync

character, Sync Mode Enable, and a Xl clock in WR4. A

data rate of 9600 baud, NRZ encoding, and a data

character length of eight bits are among the other options

that are selected in this example (Table 2).

Note that WR9 is accessed twice, first to perform a

hardware reset and again at the end of the initialization

sequence to enable the interrupts. The programming

sequence depicted in Table 2 establishes the necessary

parameters for the receiver and the transmitter so that,

when enabled, they are ready to perform communication

tasks. To avoid internal race and false interrupt conditions,

it is important to initialize the registers in the sequence

depicted in this application note.

Table 1. Register Map

Address

(hex) Write Register Read Register

FE01 WR0B RR0B

FE03 WR1B RR1B

FE05 WR2 RR2B

FE07 WR3B RR3B

FE09 WR4B

FE0B WR5B

FE0D WR6B

FE0F WR7B

FE11 B DATA B DATA

FE13 WR9

FE15 WR10B RR10B

FE17 WR11B

FE19 WR12B RR12B

FE1B WR13B RR13B

FE1D WR14B

FE1F WR15B RR15B

FE21 WR0A RR0A

FE23 WR1A RR1A

FE25 WR2 RR2A

FE27 WR3A RR3A

FE29 WR4A

FE2B WR5A

FE2D WR6A

FE2F WR7A

FE31 A DATA A DATA

FE33 WR9

FE35 WR10A RR10A

FE37 WR11A

FE39 WR12A RR12A

FE3B WR13A RR13A

FE3D WR14A

FE3F WR15A RR15A

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