Zilog Z16C35 Bedienungsanleitung PDF herunterladen (Seite 24)

ISCC

User Manual

UM011002-0808

In Shift Right Mode, bits 0-1 in WR0A controls which bits will be decoded to form the

state of the Shift Right/Shift Left bit is not known.

The register address is decoded from AD4-AD0. The Shift Right/Shift Left bit is written

via command to make the software writing to WR0 independent of the state of the Shift

Right/Shift Left bit.

AD4-AD0 is the actual register address and AD0

determines the channel se

lection (A//B).

The register map is shown in Table 2-3.

Because the ISCC SCC Cell does not contain 16 read registers, the decoding of the read

registers is not complete; this is indicated in Table 2

-2 and Table 2-3 by parentheses

around the register name. These addresses may also be used to access the read registers.

Note also that in the multiplexed bus mode, only one WR2 and

WR9 are shown in the

address map; these registers may be written from either SCC cell channel.

Table 2–2. SCC Cell Address Map, Multiplexed Bus Mode, Shift Left

Address AD5-AD1 Write Read

10000 WR0A RR0A

10001 WR1A RR1A

10010 WR2 RR2A

10011 WR3A RR3A

10100 WR4A (RR0A)

10101 WR5A (RR1A)

10110 WR6A (RR2A)

10111 WR7A (RR3A)

11000 WR8A RR8A

11001 WR9 (RR13A)

11010 WR10A RR10A

11011 WR11A (RR15A)

11100 WR12A RR12A

11101 WR13A RR13A

11110 WR14A (RR10A)

11111 WR15A RR15A

Note: The above table applies to Channel “B” also.

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