Zilog Z16C35 Bedienungsanleitung PDF herunterladen (Seite 43)

ISCC

User Manual

UM011002-0808

counter dependent upon which region the transition on the receive data input occurred.

This is shown in Figure 3-7.

Figure 3–10. DPLL Operation in the FM Mode

In FM mode, the transmit clock and receive clock outputs from the DPLL are not in phase.

This is necessary to make the transmit and receive bit cell boundaries coincide, since the

receive clock must sample the data one-fourth and three-fourths of the way through the bit

cell.

Ordinarily, a bit cell boundary will occur between count 15 or count 16, and the DPLL

receive output will cause the data to be sampled at one-fourth and

three-fourths of the way

through the bit cell.

However, four variations may happen:

4. The DPLL actually allows the transition marking a bit-cell boundary to occur any-

where during the second ha

lf of count 15 or the first half of count 16, without making

a correction to its count cycle.

5. If t

he transition marking a bit cell boundary occurs

between the middle of count 16

and the middle of count 19, the DPLL is sampling the data too early in the bit cel

l. In

response to this, the DPLL extends its count by 1 during the next 0 to 31 counting

cycle, which effectively moves the receive clock edges closer to where they should be.

Any transitions occurring between the middle of count 19 in one cycle and the middle of

count 12

during the next cycle are ignored by the DPLL. This is necessary to guarantee

that any data transitions in the bit cells will not cause an adjustment to the counting cycle.

6. If no transition occurs between the middle of count 12 and the middle of count 19, the

DPLL is probably not locked onto the data properly. When the DPLL

misses an edge,

the One Clock Missing bit is RR10, it is set to “1” and latched. It will hold this value

until a Reset missing Clock command is issued in WR14 or until the DPLL is disabled

Ignored

No Change No Change

Bit Cell

Count

Correction

RX DPLL Out

+1 -1

TX DPLL Out

118 19 201716 21 22 23 24 25 26 27 28 29 30 31 2 3 4 5 7 8 9 12 13 141110 150

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