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UM008007-0715 Z80 Instruction Description

Z80 CPU

User Manual

297

INIR

Operation

(HL) ← (C), B ← B – 1, HL ← HL +1

Op Code

INIR

Operands

None.

Description

The contents of Register C are placed on the bottom half (A0 through A7) of the address

bus to select the I/O device at one of 256 possible ports. Register B is used as a byte coun-

ter, and its contents are placed on the top half (A8 through A15) of the address bus at this

time. Then one byte from the selected port is placed on the data bus and written to the

CPU. The contents of the HL register pair are placed on the address bus and the input byte

is written to the corresponding location of memory. Then register pair HL is incremented,

the byte counter is decremented. If decrementing causes B to go to 0, the instruction is ter-

minated. If B is not 0, the Program Counter is decremented by two and the instruction

repeated. Interrupts are recognized and two refresh cycles execute after each data transfer.

If B is set to 0 prior to instruction execution, 256 bytes of data are input.

If B ≠ 0:

If B = 0:

M Cycles T States 4 MHz E.T.

5 21 (4, 5, 3, 4, 5) 5.25

M Cycles T States 4 MHz E.T.

4 16 (4, 5, 3, 4) 4.00

11 0 01111

10 1 10010

Note:

1 2 ... 304 305 306 307 308 309 310 311 312 313 314 ... 325 326

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Zilog Z08470 Bedienungsanleitung Seite 309