Zilog Z08470 Bedienungsanleitung PDF herunterladen (Seite 248)

100

101

Z80 Instruction Set UM008007-0715

236

Z80 CPU

User Manual

RLD

Operation

Op Code

RLD

Operands

Description

The contents of the low-order four bits (bits 3, 2, 1, and 0) of the memory location (HL)

are copied to the high-order four bits (7, 6, 5, and 4) of that same memory location; the

previous contents of those high-order four bits are copied to the low-order four bits of the

Accumulator (Register A); and the previous contents of the low-order four bits of the

Accumulator are copied to the low-order four bits of memory location (HL). The contents

of the high-order bits of the Accumulator are unaffected.

(HL) refers to the memory location specified by the contents of the HL register pair.

Condition Bits Affected

S is set if the Accumulator is negative after an operation; otherwise, it is reset.

Z is set if the Accumulator is 0 after an operation; otherwise, it is reset.

H is reset.

M Cycles T States 4 MHz E.T.

5 18 (4, 4, 3, 4, 3) 4.50

47 03 47 03

11 0 01111

01 0 11111

Note:

1 2 ... 243 244 245 246 247 248 249 250 251 252 253 ... 325 326

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