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UM018809-0611 AND Instruction

ZNEO

CPU Core

User Manual

Flags are set based on the memory destination size, or 32 bits for register destinations.

Syntax and Opcodes

Instruction, Operands Word 0 Word 1 Word 2

AND Rd, #imm32 {AAAH, Rd} imm[31:16] imm[15:0]

AND Rd, #uimm16 {AA2H, Rd} uimm16

AND Rd, Rs {A2H, Rs, Rd}

AND Rd, addr16 {724H, Rd} addr16

AND Rd, addr32 {72CH, Rd} addr[31:16] addr[15:0]

AND Rd, soff13(Rs) {7AH, Rs, Rd} {100B, soff13}

AND addr16, Rs {727H, Rs} addr16

AND addr32, Rs {72FH, Rs} addr[31:16] addr[15:0]

AND (Rd), #imm32 {ABAH, Rd} imm[31:16] imm[15:0]

AND (Rd), #simm16 {AD2H, Rd} simm16

AND soff13(Rd), Rs {7AH, Rs, Rd} {111B, soff13}

AND.W addr16, Rs {726H, Rs} addr16

AND.W addr32, Rs {72EH, Rs} addr[31:16] addr[15:0]

AND.W (Rd), #imm16 {AB2H, Rd} imm16

AND.W soff13(Rd), Rs {7AH, Rs, Rd} {110B, soff13}

AND.SW Rd, addr16 {723H, Rd} addr16

AND.SW Rd, addr32 {72BH, Rd} addr[31:16] addr[15:0]

AND.SW Rd, soff13(Rs) {7AH, Rs, Rd} {011B, soff13}

AND.UW Rd, addr16 {722H, Rd} addr16

AND.UW Rd, addr32 {72AH, Rd} addr[31:16] addr[15:0]

AND.UW Rd, soff13(Rs) {7AH, Rs, Rd} {010B, soff13}

AND.B addr16, Rs {725H, Rs} addr16

AND.B addr32, Rs {72DH, Rs} addr[31:16] addr[15:0]

AND.B (Rd), #imm8 {AD9H, Rd} {xH, x010B, imm8}

AND.B soff13(Rd), Rs {7AH, Rs, Rd} {101B, soff13}

AND.SB Rd, addr16 {721H, Rd} addr16

AND.SB Rd, addr32 {729H, Rd} addr[31:16] addr[15:0]

AND.SB Rd, soff13(Rs) {7AH, Rs, Rd} {001B, soff13}

AND.UB Rd, addr16 {720H, Rd} addr16

AND.UB Rd, addr32 {728H, Rd} addr[31:16] addr[15:0]

AND.UB Rd, soff13(Rs) {7AH, Rs, Rd} {000B, soff13}

Note:

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