Zilog Z16F2810 Bedienungsanleitung PDF herunterladen (Seite 24)

Architectural Overview UM018809-0611

ZNEO

CPU Core

User Manual

•

For LD and LEA instructions, a delay cycle is inserted if a register is loaded immedi-

ately before it is used for the base address in a register-indirect instruction.

•

If execution of an instruction ends before all the next instruction words are fetched,

the Execution Unit delays for the number of cycles required by the Fetch unit to com-

plete the instruction fetch. After an ILL or TRAP instruction executes, the entire next

instruction must be fetched.

For details about wait states, refer to the ZNEO product specification that is specific to

your device .

Control Registers

The ZNEO CPU and internal peripheral control registers are accessed in the I/O memory

space starting at

FF_E000H (24-bit address space devices). Table 2 lists control registers

common to all Zilog devices that incorporate the ZNEO CPU. In this table, “X” indicates

an undefined hex digit value.

For complete information about peripheral control registers for a particular device, refer to

the device specific Product Specification.

I/O memory locations can be accessed using a 16 bit address operand. For more details, see

the Direct Memory Addressing section on page 29.

Table 2. Control Registers

Address (Hex) Register Description Mnemonic

Reset Value

(Hex)

FF_E004–FF_E007 Program Counter Overflow PCOV FFFFFFFF

FF_E008–FF_E00B Reserved — xxxxxxxx

FF_E00C–FF_E00F Stack Pointer Overflow SPOV 00000000

FF_E010 Flags FLAGS xx

FF_E011 Reserved — xx

FF_E012 CPU Control CPUCTL FF

Note:

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 215 216

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Zilog Z16F2810 Bedienungsanleitung Seite 24