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UM018809-0611 Operand Addressing

ZNEO

CPU Core

User Manual

Depending on the instruction, register-indirect addressing can be used for either the source

or destination operand, but a destination’s effective address must be a writable memory or

I/O location. The range allowed for the signed offset depends on the instruction used. For

the LD, CLR, CPZ, CPCZ, INC, and DEC instructions, the register-indirect offset range is

–4,096 to +4,095. For other instructions that accept an indirect offset, the range is –8,192

to +8,191.

For allowed JP and CALL offsets, see the Jump Addressing section on page 39.

Several register-indirect instructions have alternate opcodes that do not accept an offset,

and therefore use fewer opcode words. When the offset is omitted in a register-indirect

operand, the ZNEO CPU uses the shorter instruction opcode if one is available.

Loading an Effective Address

The following assembly language statement is a an example of how you can initialize a

LD R6, #FFFFB002H

Addresses in the range FFFF_8000H to FFFF_FFFFH are common because that is where

I/O memory and internal RAM are addressed, but using a 32-bit LD to initialize a register

Figure 8. Register-Indirect Memory Addressing Example

LD.UB R10,4(R12)

42H

FFFF_7006H

R12FFFF_7002H

4 + FFFF_7002H

32-Bit ALU Registers

Memory Space

Value Loaded:

42H

—

R11—

R13—

0000_0042H R10

(Effective Address)

Note:

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 215 216

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