Zilog Z16F2810 Bedienungsanleitung PDF herunterladen (Seite 90)

AND Instruction UM018809-0611

ZNEO

CPU Core

User Manual

AND

Definition

Logical AND

Syntax

AND dst, src

Operation

dstdst AND src

Description

The source operand is logically ANDed with the destination operand. An AND operation stores a

1 when the corresponding bits in the two operands are both 1; otherwise the operation stores a 0.

The result is written to the destination. The contents of the source are unaffected. Table 21 sum-

marizes the AND operation.

Flags

Table 21. Truth Table for AND

dst src Result (dst)

00 0

10 0

01 0

11 1

76543210

C Z S V B CIRQE IRQE

–**0*–––

Legend

C = No change.

Z = Set to 1 if the result is zero; otherwise, set to 0.

S = Set to 1 if the result msb is 1; otherwise set to 0.

V = Cleared to 0.

B = Set to 1 if the initial destination or source value is 0; otherwise set to 0.

CIRQE = No change.

IRQE = No change.

1 2 ... 85 86 87 88 89 90 91 92 93 94 95 ... 215 216

Keine Kommentare

Zilog Z16F2810 Bedienungsanleitung Seite 90