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Z8
®
CPU
User Manual
UM001604-0108 Input/Output Ports
64
the port is not protected and can be overwritten by the Z8 CPU during the handshake
sequence. To avoid losing data, the software must not overwrite the port until the corre-
sponding interrupt request indicates that the external device has latched the data.
The software can always read Port 3 output and input handshake lines, but cannot write to
the output handshake line.
The following is the recommended setup sequence when configuring a Port for handshake
operation for the first time after a reset:
•
Load P01M or P2M to configure the port for input/output
•
Load P3 to set the Output Handshake bit to a logic 1
•
Load P3M to select HANDSHAKE mode for the port
Once a data transfer begins, the configuration of the handshake lines should not be
changed until the handshake is completed.
Figure 50 and Figure 51 on page 65 display detailed operation for the handshake
sequence.
Figure 50. Z8 Input Handshake
Valid Data
(Input To Z8)
State 1.
213
45
DAV
O
utput From Z8)
RDY
(Input To Z8)
Data on Port
Port 3 output is High, indicating that the I/O device is ready to accept data.
State 2.
The I/O device puts data on the port and then activates the DAV
input. This causes the data to be latched
.
State 3.
The Z8
®
CPU forces the Ready (RDY) output Low, signaling to the I/O device that the data has been latched.
State 4.
The I/O device returns the DAV
line High in response to RDY going Low.
State 5.
The Z8
CPU RR software must respond to the interrupt request and read the contents of the port in order for the
into the port input register and generates an interrupt request.
handshake sequence to be completed. The RDY line goes High if and only if the port has been read and
DAV
is High. This returns the interface to its initial state.
- Z8 Family of Microcontrollers 1
- UM001604-0108 2
- DO NOT USE IN LIFE SUPPORT 2
- LIFE SUPPORT POLICY 2
- As used herein 2
- Document Disclaimer 2
- Revision History 3
- Table of Contents 4
- Table of Contents 5
- Product Development Support 10
- UM001604-0108 Z8 11
- CPU Product Overview 11
- Address Space 12
- Address Space 13
- General-Purpose Registers 14
- RAM Protect 14
- Working Register Groups 14
- Error Conditions 17
- Standard Z8 Registers 22
- Expanded Z8 Registers 23
- Program Memory 26
- External Memory 27
- External Data Memory 28
- Clock Control 31
- External Clock Divide-By-Two 32
- Oscillator Control 33
- Oscillator Operation 34
- Circuit Board Design Rules 35
- Crystals and Resonators 36
- UM001604-0108 Clock 37
- Figure 19. LC Clock 37
- LC Oscillator 38
- RC Oscillator 39
- UM001604-0108 Reset 40
- Figure 22. Reset Timing 42
- User Manual 43
- Watchdog Timer 48
- Power-On Reset 49
- Input/Output Ports 50
- Input and Output Registers 51
- General I/O Mode 52
- Input/Output Ports 53
- Read/Write Operations 54
- Handshake Operation 54
- Handshake Operations 58
- General Port I/O 59
- Special Functions 68
- Port Handshake 70
- I/O Port Reset Conditions 73
- Analog Comparators 75
- Comparator Programming 78
- Comparator Operation 79
- Comparator Definitions 79
- Open-Drain Configuration 80
- Low EMI Emission 81
- Input Protection 82
- CMOS Autolatches 84
- Autolatch Model 85
- Design Considerations 85
- Counters and Timers 87
- Prescalers and Counter/Timers 88
- Counter/Timer Operation 90
- Prescaler Operations 91
- External Clock Input Mode 96
- Gated Internal Clock Mode 97
- Triggered Input Mode 97
- Cascading Counter/Timers 98
- Counters and Timers 100
- Interrupts 102
- Interrupt Sources 103
- External Interrupt Sources 104
- Internal Interrupt Sources 105
- Interrupt Initialization 106
- Interrupts 107
- Reset Conditions 116
- Power-Down Modes 117
- Power-Down Modes 118
- Stop Mode Recovery Register 119
- Serial Input/Output 122
- UART Bit-Rate Generation 123
- Serial Input/Output 124
- UART Receiver Operation 125
- Overwrites 126
- Framing Errors 126
- Transmitter Operation 127
- UART Reset Conditions 129
- Serial Peripheral Interface 129
- SPI Operation 132
- SPI Compare 132
- SPI Clock 132
- External Interface 138
- External Interface 139
- External Stacks 140
- Data Memory 141
- Bus Operation 141
- Address Strobe 143
- Data Strobe 143
- Extended Bus Timing 144
- Instruction Timing 145
- Reset Conditions 147
- Instruction Set 148
- Instruction Set 149
- Processor Flags 151
- Zero Flag 152
- Sign Flag 152
- Overflow Flag 152
- Decimal Adjust Flag 152
- Condition Codes 153
- Notation and Binary Encoding 154
- Assembly Language Syntax 156
- Instruction Summary 157
- Op Code Map 163
- Instruction Description 164
- Instruction Description 165
- Add With Carry 168
- Call Procedure 171
- Complement Carry Flag 173
- Complement 175
- Decimal Adjust 179
- Decrement 182
- Decrement Word 185
- Disable Interrupts 187
- Enable Interrupts 188
- Increment 190
- Increment Word 192
- Interrupt Return 194
- Jump Relative 197
- Load Constant 202
- Load Constant Autoincrement 204
- Load External Data 206
- No Operation 210
- Logical AND 211
- Logical OR 214
- Logical Exclusive OR 217
- Reset Carry Flag 224
- C D7D6D5D4D3D2D1D0 226
- CD7 D6 D5 D4 D3 D2 D1 D0 230
- Set Carry Flag 234
- Set Register Pointer 235
- Subtract 241
- Subtract With Carry 244
- Swap Nibbles 247
- Test Complement Under Mask 249
- Test Under Mask 252
- Watchdog Timer 255
- UM001604-0108 Index 257
- Customer Support 260
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