Zilog Z86193 Bedienungsanleitung PDF herunterladen (Seite 102)

CPU

User Manual

UM001604-0108 Interrupts

Interrupts

CPU allows 6 different interrupts from a variety of sources; up to four external inputs,

the on-chip Counter/Timer(s), software, and serial I/O peripherals. These interrupts can be

masked and their priorities are set by using the Interrupt Mask and the Interrupt Priority

Registers. All six interrupts can be globally disabled by resetting the master Interrupt

Enable, bit 7 in the Interrupt Mask Register, with a Disable Interrupt (DI) instruction.

Interrupts are globally enabled by setting bit 7 with an Enable Interrupt (EI) instruction.

There are three interrupt control registers: the Interrupt Request Register (IRQ), the Inter-

rupt Mask register (IMR), and the Interrupt Priority Register (IPR). Figure 90 displays

addresses and identifiers for the interrupt control registers. Figure 91 on page 96 displays

the block diagram illustrating the Interrupt Mask and Interrupt Priority logic. The Z8 fam-

ily supports both vectored and polled interrupt handling.

Figure 90. Interrupt Control Registers

HEX

Interrupt Mask

Interrupt Request

Interrupt Priority

Identifier

FBh

FAh

F9h

IMR

IRQ

IPR

1 2 ... 97 98 99 100 101 102 103 104 105 106 107 ... 259 260

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Zilog Z86193 Bedienungsanleitung Seite 102