Zilog Z86193 Bedienungsanleitung PDF herunterladen (Seite 182)

CPU

User Manual

UM001604-0108 Instruction Description

175

Decrement

Syntax

DEC dst

Instruction Format

Operation

dst ← dst–1

The contents of the destination operand are decremented by one.

Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the

destination Working Register operand is specified by adding

1110b (Eh) to the high nibble

of the operand. For example, if Working Register R12 (CH) is the destination operand, then

ECh is used as the destination operand in the Op Code.

Example 1

If Working Register R10 contains 2A%, the statement:

DEC R10

Op Code: 00 EA

leaves the value 29h in Working Register R10. The Z, V, and S Flags are cleared.

Example 2

If Register B3h contains CBh, and Register CBh contains 01h, the statement:

DEC @B3h

Op Code: 01 B3

leaves the value 00h in Register CBh. The Z Flag is set, and the V and S Flags are cleared.

Cycles

OPC

(Hex)

Address

Mode dst

OPC dst

600R

601IR

Flag Description

C Unaffected

Z Set if the result is zero; cleared otherwise

S Set if the result of bit 7 is set (negative); cleared otherwise

V Set if arithmetic overflow occurs; cleared otherwise

D Unaffected

H Unaffected

Edst

Note:

1 2 ... 177 178 179 180 181 182 183 184 185 186 187 ... 259 260

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