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U
SER
'
S
M
ANUAL
Z
ILOG
The four instruction formats are shown in Tables A-1
through A-4. Within each format, several different configu-
rations are possible, depending on whether the instruction
involves addressing mode escape bytes, addresses, dis-
placements, or immediate data. In Table A-1 through A-4,
the symbol “A.esc” is used to indicate the presence of an
addressing mode escape byte, “O.esc” is used to indicate
the presence of an opcode escape byte, “disp.” is an
abbreviation for displacement and “addr.” is an abbrevia-
tion for address.
Table A-1. Format 1 Instructions Encodings
Instruction Format Assembly Hexadecimal
Opcode LD A,C 79
Opcode 2-byte Address LD A,(addr) 3A addr (L) addr (H)
Opcode 1-byte Displacement DJNZ addr 10 disp
Opcode Immediate LD E,n 1E n
A.esc Opcode 2-byte Address LD IX,(addr) DD 2A addr (L) addr (H)
A.esc Opcode 1-byte Displacement LD A, (IX+d) DD 7E disp
A.esc Opcode Immediate LD IX,nn DD 21 n(L) n(H)
A.esc Opcode 1-byte Displacement Immediate LD (IY+d),n FD 36 d n
Note: “A.esc” is an addressing mode escape byte, and either 0DDH or 0FDH.
Table A-2. Format 2 Instructions Encodings
Instruction Format Assembly Hexadecimal
Opcode LD A,C 79
O.esc Opcode Immediate (1 byte) TST n ED 64 n
O.esc Opcode Immediate (2 bytes) LD (BC),nn ED 06 n(L) n(H)
O.esc Opcode Address (2 bytes) LD BC,(addr) ED 4B addr (L) addr (H)
O.esc Opcode Displacement (1 byte) CALR e ED CD e
O.esc Opcode Displacement (2 bytes) JR ee DD 18 d(L) d(H)
O.esc Opcode Displacement (3 bytes) JR eee FD 18 d(L) d(M) d(H)
Note: “O.esc” is an opcode escape byte, and either 0DDH, 0EDH or 0FDH.
Table A-3. Format 3 Instruction Encoding
CB Opcode RLC (HL) CB 06
A.esc CB 1 Byte Displacement Opcode RLC (IX+d) DD CB d 06
Note: “A.esc” is an addressing mode escape byte, and either 0DDH or 0FDH.
Table A-4. Format 4 Instruction Encoding
ED CB Opcode RRCW BC ED CB 08
ED CB Opcode Immediate MULTW nn ED CB 97 n(L) n(H)
- Z80380 CPU 1
- 'S MANUAL 1
- CHAPTER 1 3
- 1.1 INTRODUCTION (Continued) 4
- 1.2 CPU ARCHITECTURE 5
- 1.2.1 Modes of Operation 5
- 1.2.2 Address Spaces 5
- 1.2.3 Data Types 6
- 1.2.4. Addressing Modes 6
- 1.2.5. Instruction Set 6
- 1.2.6 Exception Conditions 6
- 1.3.1 High Throughput 7
- (Continued) 8
- 1.4 SUMMARY 8
- SER'S MANUAL 10
- 2.4 MEMORY ADDRESS SPACE 12
- USER'S MANUAL 15
- DC-8297-03 15
- CHAPTER 2 16
- CHAPTER 3 23
- 3.2 DECODER DIRECTIVES 24
- CHAPTER 4 26
- 4.2.3 Indirect Register (IR) 27
- 4.2.4 Direct Address (DA) 28
- 4.2.5 Indexed (X) 29
- 4.3 DATA TYPES 34
- CHAPTER 5 35
- 5.2.7 Condition Codes 37
- SWAP, and PUSH/POP Group 41
- 5.5.8 Program Control Group 46
- 5.5.11 CPU Control Group 50
- 5.5.12 Decoder Directives 51
- 5.7 EXECUTION TIME 52
- ADD WITH CARRY (BYTE) 54
- ADD WITH CARRY (WORD) 55
- ADD (BYTE) 57
- ADD (WORD) 58
- ADD TO STACK POINTER (WORD) 59
- AND (BYTE) 61
- AND (WORD) 62
- BIT TEST 63
- BANK TEST 64
- CALL RELATIVE 66
- COMPLEMENT CARRY FLAG 67
- COMPARE (BYTE) 68
- COMPARE (WORD) 69
- COMPARE AND DECREMENT (BYTE) 70
- COMPARE AND INCREMENT (BYTE) 72
- COMPLEMENT ACCUMULATOR 74
- COMPLEMENT HL REGISTER (WORD) 75
- DECIMAL ADJUST ACCUMULATOR 76
- DECODER DIRECTIVE 77
- DECREMENT (BYTE) 78
- DECREMENT (WORD) 79
- DISABLE INTERRUPTS 80
- DIVIDE UNSIGNED (WORD) 81
- ENABLE INTERRUPTS 83
- EXCHANGE REGISTER (WORD) 86
- EXCHANGE WITH ACCUMULATOR 89
- EXTEND SIGN (BYTE) 91
- EXTEND SIGN (WORD) 92
- INTERRUPT MODE SELECT 97
- INPUT (BYTE) 98
- INPUT (WORD) 99
- INPUT ACCUMULATOR 100
- INPUT (FROM PAGE 0) 101
- INCREMENT (BYTE) 104
- INCREMENT (WORD) 105
- INPUT AND DECREMENT (BYTE) 106
- INPUT AND DECREMENT (WORD) 107
- INPUT AND INCREMENT (BYTE) 110
- INPUT AND INCREMENT (WORD) 111
- JUMP RELATIVE 115
- LOAD ACCUMULATOR 116
- LOAD IMMEDIATE (BYTE) 117
- LOAD IMMEDIATE (WORD) 118
- LOAD REGISTER (BYTE) 120
- LOAD REGISTER (WORD) 121
- LOAD STACK POINTER 123
- LOAD I REGISTER (WORD) 126
- LOAD CONTROL REGISTER (BYTE) 127
- LOAD AND DECREMENT (BYTE) 130
- LOAD AND DECREMENT (WORD) 131
- LOAD AND INCREMENT (BYTE) 134
- LOAD AND INCREMENT (WORD) 135
- MULTIPLY UNSIGNED (BYTE) 138
- MODE TEST 139
- MULTIPLY (WORD) 140
- MULTIPLY UNSIGNED (WORD) 141
- NEGATE ACCUMULATOR 142
- NEGATE HL REGISTER (WORD) 143
- NO OPERATION 144
- OR (BYTE) 145
- OR (WORD) 146
- OUTPUT DECREMENT MEMORY 147
- OUTPUT INCREMENT MEMORY 151
- OUTPUT (BYTE) 155
- OUTPUT (WORD) 156
- OUTPUT ACCUMULATOR 157
- OUTPUT (TO PAGE 0) 158
- OUTPUT AND DECREMENT (BYTE) 161
- OUTPUT AND DECREMENT (WORD) 162
- OUTPUT AND INCREMENT (BYTE) 163
- OUTPUT AND INCREMENT (WORD) 164
- POP ACCUMULATOR 165
- POP CONTROL REGISTER 166
- POP REGISTER 167
- PUSH ACCUMULATOR 168
- PUSH CONTROL REGISTER 169
- PUSH IMMEDIATE 170
- PUSH REGISTER 171
- RESET BIT 172
- RESET CONTROL BIT 173
- RETURN FROM BREAKPOINT 175
- RETURN FROM INTERRUPT 176
- ROTATE LEFT (BYTE) 178
- ROTATE LEFT (WORD) 179
- ROTATE LEFT (ACCUMULATOR) 180
- ROTATE LEFT CIRCULAR (BYTE) 181
- ROTATE LEFT CIRCULAR (WORD) 182
- ROTATE LEFT DIGIT 184
- ROTATE RIGHT (BYTE) 185
- ROTATE RIGHT (WORD) 186
- ROTATE RIGHT (ACCUMULATOR) 187
- ROTATE RIGHT CIRCULAR (BYTE) 188
- ROTATE RIGHT CIRCULAR (WORD) 189
- ROTATE RIGHT DIGIT 191
- SUBTRACT WITH CARRY (BYTE) 193
- SUBTRACT WITH CARRY (WORD) 194
- SET CARRY FLAG 196
- SET CONTROL BIT 198
- SHIFT LEFT ARITHMETIC (BYTE) 199
- SHIFT LEFT ARITHMETIC (WORD) 200
- SHIFT RIGHT ARITHMETIC (BYTE) 202
- SHIFT RIGHT ARITHMETIC (WORD) 203
- SHIFT RIGHT LOGICAL (BYTE) 204
- SHIFT RIGHT LOGICAL (WORD) 205
- SUBTRACT (BYTE) 206
- SUBTRACT (WORD) 207
- TEST (BYTE) 211
- TEST I/O PORT 212
- EXCLUSIVE OR (BYTE) 213
- EXCLUSIVE OR (WORD) 214
- CHAPTER 6 215
- 6.2 INTERRUPTS (Continued) 216
- 6.2.2 Interrupt Control 216
- 6.3 TRAP INTERRUPT 218
- 6.7 RETI INSTRUCTION 220
- CHAPTER 7 222
- APPENDIX A 225
- APPENDIX B 228
- APPENDIX C 243
- APPENDIX D 258
- APPENDIX E 262
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