Zilog Z80230 Bedienungsanleitung PDF herunterladen (Seite 173)

SCC/ESCC

User Manual

UM010903-0515 Register Descriptions

166

Write Register 11

Bit 7: RTxC-XTAL//NO XTAL select bit

This bit controls the type of input signal the SCC expects to see on the /RTxC pin. If this bit is set

to 0, the SCC expects a TTL-compatible signal as an input to this pin. If this bit is set to 1, the SCC

connects a high-gain amplifier between the /RTxC and /SYNC pins in expectation of a quartz

crystal being placed across the pins.

The output of this oscillator is available for use as a clocking source. In this mode of operation, the

/SYNC pin is unavailable for other use. The /SYNC signal is forced to zero internally. A hardware

reset forces /NO XTAL. (At least 20 ms should be allowed after this bit is set to allow the oscilla-

tor to stabilize.)

Bits 6 and 5: Receiver Clock select bits 1 and 0

These bits determine the source of the receive clock as listed in Table on page 166. They do not

interfere with any of the modes of operation in the SCC, but simply control a multiplexer just

before the internal receive clock input. A hardware reset forces the receive clock to come from the

/RTxC pin.

Bits 4 and 3: Transmit Clock select bits 1 and 0.

These bits determine the source of the transmit clock as listed in Table . They do not interfere with

any of the modes of operation of the SCC, but simply control a multiplexer just before the internal

transmit clock input. The DPLL output that is used to feed the transmitter in FM modes lags by 90

degrees the output of the DPLL used by the receiver. This makes the received and transmitted bit

cells occur simultaneously, neglecting delays. A hardware reset selects the /TRxC pin as the

source of the transmit clocks.

Receive Clock Source

Bit 6 Bit 5 Receive Clock

00/RTxC Pin

01/TRxC Pin

1 0 BR Output

1 1 DPLL Output

1 2 ... 168 169 170 171 172 173 174 175 176 177 178 ... 393 394

Keine Kommentare

Zilog Z80230 Bedienungsanleitung Seite 173