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SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
148
Write Register 3 (Receive Parameters and Control)
This register contains the control bits and parameters for the receiver logic as displayed in Figure .
On the ESCC and 85C30, with the Extended Read option enabled, this register may be read as
RR9.
Write Register 3
Bits 7 and 6: Receiver Bits/Character
The state of these two bits determines the number of bits to be assembled as a character in the
received serial data stream. The number of bits per character can be changed while a character is
being assembled, but only before the number of bits currently programmed is reached. Unused bits
in the Received Data Register (RR8) are set to 1 in asynchronous modes. In Synchronous and
SDLC modes, the SCC merely transfers an 8-bit section of the serial data stream to the Receive
FIFO at the appropriate time. Table lists the number of bits per character in the assembled charac-
ter format.
Receive Bits per Character
D7 D6 Bits/Character
005
017
106
118
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 3
Rx Enable
0 0 Rx 5 Bits/Character
0 1 Rx 7 Bits/Character
1 0 Rx 6 Bits/Character
1 1 Rx 8 Bits/Character
Sync Character Load Inhibit
Address Search Mode (SDLC)
Rx CRC Enable
Enter Hunt Mode
Auto Enables
- SCC/ESCC 1
- UM010903-0515 2
- Revision History 3
- Table of Contents 4
- SCC’s Capabilities 9
- User Manual 13
- SCC Block Diagram 13
- Pin Descriptions 14
- Z85X30 DIP Pin Assignments 17
- Z85X30 PLCC Pin Assignments 18
- Z80X30 DIP Pin Assignments 19
- Interfacing the SCC/ESCC 24
- Z80X30 Write Cycle Timing 25
- Z80X30 Register Access 28
- Z80C30 Register Enhancement 31
- Z80230 Register Enhancements 32
- Z80X30 Reset 33
- Z85X30 Interface Timing 34
- Z85X30 Read Cycle Timing 35
- Z85X30 Write Cycle Timing 35
- D7-D0 Vector 36
- Z85X30 Register Access 37
- Z85C30 Register Enhancement 39
- Z85X30 Reset 41
- Interface Programming 42
- I/O Programming Introduction 43
- Interrupts 43
- External/Status Channel A 44
- Receive Channel B 44
- Transmit Channel B 44
- * Always 0 In B Channel 47
- Daisy-Chain Resolution 48
- Interrupt Acknowledge 51
- The Receiver Interrupt 52
- Receive Interrupts Disabled 53
- Conditio 56
- External/Status Interrupts 63
- Break/Abort 65
- Transmit Underrun/EOM 65
- CTS/DCD 66
- Zero Count 66
- Sync/Hunt 66
- Block/DMA Transfer 67
- SYNC Modes 68
- ASYNC Modes 68
- Wait On Receive 69
- DMA Requests 70
- DMA Request On Receive 74
- AD7-AD0 Receive DataWR8 75
- Test Functions 76
- Introduction 78
- Baud Rate Generator 78
- Data Encoding/Decoding 81
- Clock Selection 90
- Clock Multiplexer 92
- BRG Clock Source = /RTXC 93
- Crystal Oscillator 94
- Data Communication Modes 95
- Transmit Data Path 96
- Asynchronous Mode 99
- Asynchronous Transmit 100
- Asynchronous Receive 103
- Asynchronous Initialization 105
- Reg Bit No Description 107
- WR4 3 (=0) select sync mode 107
- State Changes in One 113
- /RTxC Clock Cycle 113
- SDLC Transmit 121
- SDLC Receive 127
- SDLC Frame Status FIFO 133
- Frame Status FIFO Circuitr 135
- Interface 135
- SDLC Loop Mode 137
- SDLC Loop Mode Receive 140
- SDLC Loop Mode Transmit 140
- Register Descriptions 143
- Write Registers 145
- Definition) 149
- Z85X30 Register Map 151
- Time Constant 175
- Clock Frequency 175
- Read Registers 181
- Read Register 1 185
- Read Register 2 187
- Read Register 3 188
- Read Register 8 191
- Read Register 10 192
- Read Register 12 193
- Read Register 13 194
- Read Register 15 194
- Application Notes 195
- Abstract 217
- Features 217
- Discussion 217
- Interfaces 218
- Z180 to Memory Interface 218
- EPROM Interface 220
- SRAM Interface 222
- SRAM Read Cycle 222
- SRAM Write Cycle 223
- Memory Interface Logic 223
- Physical Memory Address Map 225
- Z180 to I/O Interface 226
- Z180 I/O Write Cycle Timing 227
- Z180 to SCC Interface 230
- CPU Hardware Interfacing 230
- Data Bus Signals 230
- System Control Signals 230
- Interrupt Control 231
- SCC I/O Operation 231
- Read Cycle Timing 231
- Write Cycle Timing 232
- SCC Interrupt Operation 232
- Input/Output Cycles 234
- Z180 MPU to SCC Interface 234
- SCC I/O Read/Write Cycle 235
- I/O Read Cycle 235
- I/O Write Cycle 235
- Using EPLD 242
- System Checkout 243
- Software Considerations 244
- SCC Read Cycle Proof 244
- SCC Write Cycle Proof 244
- Interrupt Acknowledge Cycle 244
- (Continued) 246
- Summary 256
- General Description 257
- Processor 258
- Address Map 260
- (PBA)+511 269
- Serial Interfacing 270
- DMA channel 272
- Jumper Summary 276
- Control EPLD for 186 Board 278
- SCC EPLD for 186 Board 279
- DMA EPLD for 186 Board 280
- NMI Field for 186 Board 281
- Operation 295
- ESCC Controller 318
- Questions and Answers 382
- Customer Support 394
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