Zilog EZ80190 Bedienungsanleitung PDF herunterladen (Seite 27)

eZ80190 Development Kit

User Manual

UM014108-0810 Operational Description

I/O Functionality

The

eZ80Acclaim!

Development Platform provides additional functional-

ity, featuring general-purpose port, an LED matrix, a modem reset, and two

user triggers. These functions are memory-mapped with an address decoder

based on the Generic Array Logic GAL22lV10D (U15) device manufac-

tured by Lattice Semiconductor, and a bidirectional latch (U16). Addition-

ally, U15 is used to decode addresses for access to the 7 x 5 LED matrix.

Table 5. CPU Bus Connector J8*

Signal Pin # Function Direction

A[0:7] 3–10 Address Bus, Low Byte Output

A[8:15] 13–20 Address Bus, High Byte Output

A[16:23] 23–30 Address Bus, Upper Byte Output

33 Read Signal Output

RESET

35 Push Button Reset Output

BUSACK

37 CPU Bus Acknowledge Signal Output

NMI

39 Nonmaskable Interrupt Input

D[0:7] 43–50 Data Bus Bidirectional

CS[0:3] 53–56 Chip Selects Output

MREQ

57 Memory Request Output

34 Write Signal Output

INSTRD

36 Instruction Fetch Output

BUSREQ

38 CPU Bus Request signal Input

PHY 40 Clock output of the CPU Output

Note: *All of the signals except BUSACK and INSTRD are driven by low-

voltage CMOS technology (LVC) drivers.

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